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Personal IRIS and Data Station Server 4D/35

High Performance CPU Technology for the Personal IRIS

Using the latest microprocessor from MIPS Computer Systems and advanced VLSI gate arrays, Silicon Graphics has redesigned the Personal IRIS CPU architecture. Built to support release 3.3 of Silicon Graphics' system software, the 4D/35 offers a broad range of performance enhancements while providing a completely compatible upgrade path for existing Personal IRIS systems.

Increased Overall System Performance The 4D/35 incorporates MIPS Computer Systems' 33 MHz R3000A CPU and R3010 FPU into the Personal IRIS product family. The fast CPU clock rate is complemented by a fast system bus (increased from 10 MHz to 30 MHz), an innovative memory subsystem, and expanded peripheral I/O capabilities. These features combine to deliver the highest available R3000 uniprocessor performance.

New CPU Architecture

Architectural Diagram

The 4D/35 offers full support for the R3000A feature set, including block cache refills, instruction streaming and partial cache writes. Additionally, a multi-level CPU write buffer (resident on a Silicon Graphics proprietary VLSI gate array) significantly enhances CPU write throughput and maximizes MFLOP performance. Overall CPU cache size has been increased to 64K instruction and 64K data. The fastest member of the Personal IRIS family, the 4D/35, is rated at more than 27 MIPS (VAX Dhrystone) and 5 MFLOPS (double precision) representing a 70 percent MIPS increase and a 200 percent MFLOP improvement over previous systems.

Enhanced High-Speed Memory

The 4D/35 offers users access to 128 MB of very high throughput main memory. An innovative memory architecture results in an order-of-magnitude increase in memory bandwidth over previous Personal IRIS systems. This enhancement, added to the R3000A implementation, faster system bus and expanded I/O capabilities, significantly improves application performance.

Memory is user installable and available from a minimum of 8 MB, up to a 128 MB maximum.

Greater I/O Bandwidth

Peripheral management is handled through a highly integrated peripheral controller and a Motorola digital signal processor (DSP). The peripheral controller has a FIFO buffer for each of four independent channels. The buffers accumulate data from slow peripherals and transfer it directly into main memory. A burst mode transfer scheme allows data to be moved with very low system bus overhead. As a result, raw peripheral performance is increased and the impact of peripheral interactions on the main processor is minimized. High rates of peripheral activity can be achieved with no impact on computational or graphics performance. The DSP processes audio signals and handles data transfers through four serial channels. This design also relieves the interrupt demand on the main processor, allowing the serial channels to operate at speeds in excess of 38.2 Kbaud.

Expanded I/O capability

In addition to the Ethernet, parallel, VME, and two RS-232 interfaces available on the 4D/25, the 4D/35 offers two high-speed DIN-connector serial ports. Digital audio I/O based on the AES3 serial digital interface is standard on the 4D/35. These new I/O capabilities provide the user access to a whole range of new peripherals and communication options.


               40/20               40/25 and 4D/25S     40/35 and 4D/35S
Processor      RISC 12.5 MHz	   RISC 20 MHz          RISC 33 MHz
MIPS           10                  16                   27 (est)
MFLOPS         0.9                 1.6                  5.0 (est)
Cache          8 KB/16 KB          32KB/64KB            64KB/64KB
               data/instruction    data/instruction     data/instruction
Memory Size    8-32 MB             8-32 MB              8-128 MB
VME            single-word data    single-world data    block transfer
               transfer only       transfer only        mode supported
Parallel       input only          input only           bi-directional
                                                        data transfer
Audio          basic analog        basic analog         AES3
               8-bit precision     8-bit precision      16-bit precision
               mono                mono                 stereo

Specifications are subject to change without notice. Silicon Graphics, the Silicon Graphics logo and IRIS are registered trademarks, and Personal IRIS is a trademark of Silicon Graphics, Inc.; Motorola is a registered trademark of Motorola, Inc. Copyright 1990, Silicon Graphics, Inc. All Rights Reserved.

Typed up by Ian Mapleson (mapesdhs@yahoo.com) on 01/Aug/2002
Original document code: LW-MAG-01 1000045 8/90 (August 1990)

Ian's SGI Depot: FOR SALE! SGI Systems, Parts, Spares and Upgrades

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