Using the latest microprocessor from MIPS Computer Systems and advanced VLSI gate arrays, Silicon Graphics has redesigned the Personal IRIS CPU architecture. Built to support release 3.3 of Silicon Graphics' system software, the 4D/30 and 4D/35 offer a broad range of performance enhancements while providing a completely compatible upgrade path for existing Personal IRIS systems.
Increased Overall System Performance
The 4D/30 and 4D/35 incorporate MIPS Computer Systems R3000A CPU and R3000 FPU into the Personal IRIS product family. The 4D/30 uses a 30MHz R3000A CPU and the 4D/35 uses a 35MHz R3000A CPU. The fast CPU clock rate is complemented by a fast system bus (increased from 10MHz to 30MHz), an innovative memory subsystem, and expanded peripheral I/O capabilities. These features combine to deliver the highest available R3000 uniprocessor performance.
New CPU Architecture
The 4D/30 and 4D/35 offer full support for the R3000A feature set, including block cache refills, instruction streaming and partial cache writes. Additionally, a multi-level CPU write buffer (resident on a Silicon Graphics proprietary VLSI gate array) significantly enhances CPU write throughput and maximizes MFLOP performance. Overall CPU cache size has been increased to 64K instruction and 64K data. The fastest members of the Personal IRIS family, the 4D/30 is rated at 27 MIPS (VAX Dhrystone) and 4.7 MFLOPS (double precision), and the 4D/35 is rated at 33 MIPS and 6 MFLOPS.
Enhanced High-Speed Memory
The 4D/30 and 4D/35 offer users access to 128MB of very high throughput main memory. An innovative memory architecture results in an order-of-magnitude increase in memory bandwidth over previous Personal IRIS systems. This enhancement, added to the R3000A implementation, faster system bus and expanded I/O capabilities, significantly improves application performance.
Memory is user installable and available from a minimum of 8MB, up to a maximum of 128MB.
Greater I/O Bandwidth
Peripheral management is handled through a highly integrated peripheral controller. A Motorola digital signal processor (DSP) controls the audio interface.
The peripheral controller has a FIFO buffer for each of four independent channels. The buffers accumulate data from slow peripherals and transfer it directly into main memory. A burst mode transfer scheme allows data to be moved with very low system bus overhead. As a result, raw peripheral performance is increased and the impact of peripherall interactions on the main processor is minimized. High rates of peripheral activity can be achieved with no impact on computational or graphics performance.
The DSP processes audio signals and handles data transfers through four serial channels. This design also relieves the interrupt demand on the main processor. All four serial channels can operate at speeds up to 38.4Kbaud.
Expanded I/O Capability
In addition to the Ethernet, parallel, VME, and two RS232 interfaces available on the 4D/25, the 4D/30 and 4D/35 offer two DIN-connector serial ports.
Digital audio I/O based on the AES3 serial digital interface is optional on the 4D/30 and available on the 4D/35. These new I/O capabilities provide the user access to a whole range of new peripherals and communications options.
4D/25 4D/30 4D/35 and 4D/35S Processor RISC 20MHz RISC 30MHz RISC 35MHz MIPS 16 27 33 MFLOPS 1.6 4.7 6.0 SPECmark 14 25.4 31.1 Cache 32KB/64KB d/i 64KB/64KB d/i 64KB/64KB d/i Memory Size 8 - 32MB 8 - 128MB 8 - 128MB VME single-word data block-transfer block-transfer transfer only mode supported mode supported Parallel output only bi-directional bi-directional data transfer data transfer (optional) Audio basic analog analog and serial analog and serial I/O, 8bit digital, 16bit digital, 16bit precision mono precision stereo precision stereo
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